Field of the Invention
This invention relates to source follower circuits, and more particularly to circuitry for enhancing the slew rate of a source follower circuit used for buffering an input voltage and providing the buffered input voltage to a sampling capacitor via a sampling switch.
Description of the Related Art
Transistor source follower circuits are commonly used as simple voltage buffers in applications that do not require very high linearity. The DC characteristics of source follower circuits are such that the buffered output voltage tracks the input voltage except for a voltage shift equal to the gate-to-source voltage of the source follower transistor. The advantages of source follower circuits as buffers are low device count, low noise, unconditional stability and a relatively large signal swing. However, the transient response of source follower circuits suffers from an asymmetry in the settling speed. For example, an NMOS source follower has fast settling for a low-to-high transition and slow settling for a high-to-low transition; in the latter case the settling time is limited by the available bias current. This is explained in more detail in the following paragraph.
Consider the schematic and timing diagrams shown in FIGS. 1A and 1B, respectively. In FIG. 1A, a source follower circuit is formed from an NMOS input FET M1 which is connected in series with an NMOS bias FET M2 as shown. An input voltage to be buffered (Vin) is applied to the gate of M1, a bias voltage (Vbias) is applied to the gate of M2 (causing it to conduct a current Ibias), and the output (Vout) of the source follower circuit is provided at a junction 10 of M1 and M2. In this example, Vout is sampled on a sampling capacitor Cs when switch SAMPLE is closed; the voltage on Cs is referred to as Vs.
The operation of the circuitry is shown in FIG. 1B. Within every sampling period Δt, switch SAMPLE is closed for time Δtsample while the input voltage is periodically switched between levels Vin,min and Vin,max when switch SAMPLE is open. Each time switch SAMPLE is closed, the voltage Vs on the sampling capacitor must settle from the previous sampled value to the new one. The settled voltage output levels corresponding to Vin,min and Vin,max sampled on Cs are Vs,min and Vs,max. If Vs is at a minimum voltage Vs,min, then when switch SAMPLE closes Vs increases from voltage Vs,min to a voltage Vs,max. This illustrates the relatively fast settling for a low-to-high transition. Note that the transient current pulling Vs from Vs,min to Vs,max is a function of the drive strength of M1 and can be substantially higher than the bias current Ibias. If Vs is at maximum voltage Vs,max, then when switch SAMPLE closes, Vs decreases from Vs,max to Vs,min. The settling for a high-to-low transition is significantly slower because the transient current pulling Vs from Vs,max to Vs,min (known also as the slew current Islew) is limited by the bias current Ibias provided by M2. Since Islew=Ibias=const, Vs(t) decreases linearly at a rate known as the slew rate and given by Islew/Cs. This portion of the settling time is known as slewing time. If the slewing time is assumed to be, for example, 80% of the available settling time Δtsample, then the required source follower bias current is:
                              I          bias                =                              I            slew                    =                                                                      C                  s                                ⁡                                  (                                                            V                                              s                        ,                        max                                                              -                                          V                                              s                        ,                        min                                                                              )                                                            0.8                ⁢                Δ                ⁢                                                                  ⁢                                  t                  sample                                                      .                                              (        1        )            Equation (1) shows that the bias current must be sized to achieve settling within Δtsample for the largest expected voltage swing Vs,max−Vs,min. Given randomly distributed input voltages, the signal swing will be less than that on average, but the bias current must be set high enough to satisfy the worst case. This highlights the energy inefficiency of the classic source follower circuit. It can be shown that the static and dynamic energies (E) consumed from the supply per period Δt by the source follower circuit of FIG. 1A are as follows:
                                          Static            ⁢                                                  ⁢            E                    =                                                    (                                  I                  bias                                )                            ⁢                              (                                  V                  dd                                )                            ⁢                              (                                  Δ                  ⁢                                                                          ⁢                                      t                    sample                                                  )                                      =                                                                                C                    S                                    ⁡                                      (                                                                  V                                                  s                          ,                          max                                                                    -                                              V                                                  s                          ,                          min                                                                                      )                                                  ⁢                                  V                  dd                                            0.8                                      ;                            (                  2          ⁢          a                )            Dynamic E=0(on average).  (2b)
The high-to-low transition can be improved by ‘precharging’ sampling capacitor Cs to ground before the SAMPLE switch closes; this is illustrated in FIGS. 2A and 2B. The precharging is accomplished with a switch CLR connected across capacitor Cs. As shown in FIG. 2B, switch CLR is closed —and thus Cs is precharged (or reset) to ground —before switch SAMPLE is closed. When so arranged, Cs does not have to be discharged by the source follower bias transistor M2 when Vin falls, thereby eliminating the slew-limited settling and the slow high-to-low transition exhibited by the circuit of FIG. 1A. The static and dynamic energies (E) consumed from the supply per period Δt by the source follower circuit of FIG. 2A are as follows:Static E=(Ibias)(Vdd)(Δtsample);  (3a)Dynamic E=CsVsVdd  (3b)While at first glance the static energy given by (3a) appears to be the same as (2a), it is in fact significantly lower because Ibias no longer needs to equal the slew current defined by equation (1) and is in fact much smaller (typically set so that the transconductance of M1 achieves the small-signal time constant for the targeted settling time).
The dynamic energy term given by equation (3b) is proportional to the sampled voltage on the capacitor Vs. For the largest input voltage (and hence largest Vs) the static and dynamic energy consumed by the circuit of FIG. 2A approaches that of the circuit of FIG. 1A. However, for randomly distributed input voltages between ground and the largest input voltage, the circuit of FIG. 2A is more energy efficient. Nevertheless, it still has the drawback that dynamic energy is drawn from the supply even if there is no change in Vin from sample to sample.